Semiconductor integrated circuits often incorporate hundreds of thousands of semiconductor elements on a single chip. These elements are interconnected to perform a desired function.
There are many applications that require precise delay skew control across a group of signals in the design of digital logic circuitry. Delay skew is often defined as the variation or delta in propagation delays among such a group of signals.
A source synchronous interface is an example of a general category of a type of application that often requires precise delay skew control. A source synchronous interface is a parallel data transfer bus, which typically includes a group of data signals and reference clock signals. Both the data signals and the reference clock signals need to travel through equal propagation delays and arrive at their respective destinations at the same time, to within a relatively small margin of error, in order to be sampled correctly.
One particular type of source synchronous interface is referred to as a double data rate (DDR) interface in which data is transferred on each half-cycle of the reference clock. In this type of interface, duty cycle distortion (i.e., rise time and fall time differences) also needs to be minimized to provide the optimal data sampling window when the data is sampled at the destination.
In addition to the source synchronous interface application, another area that often requires precise delay skew management is the area of clock synthesis across heterogeneous logic blocks in integrated circuits (IC) implementations. Due to the heterogeneity of different logic blocks, the various clock signals of the global clock tree may diverge into a wide variety of differences in their delay at the clock end points, disrupting logic processing across the IC.
In a typical IC design environment, the delay skew management is achieved through a tedious manual iterative manner. The process typically starts with an initial trial run with the physical design tool. It then feeds back the initial design to the design group for timing analysis to determine whether the initial design fits the requirements. If not, the process repeats again through enough iterations until the design converges to an acceptable result. Since skew requirements have to be observed across all manufacturing process ranges as well as all operating conditions such as voltage and temperature ranges (PVT), the process can be very time-consuming and the result may not be able to satisfy all PVT conditions. Improved systems and methods for reducing signal delay skew would therefore provide broad advantages for a wide range of digital circuitry.
The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter, nor does it identify any needs or problems recognized in the art.